1. Field of the Invention
The present invention relates to a data processing apparatus and a data processing method, and more specifically, to a data processing apparatus in which data to be processed is divided and processed, and a data processing method therefor.
2. Description of Related Art
In response to the need for processing a large quantity of data in recent years, improvement of speed of data processing is developed. In order to improve a processing speed, there may be a case where data processing is performed serially to attain shortening of a processing time. That is, there may be a case where a circuit configuration is simplified and thereby a cycle time is shortened.
A data processing apparatus that performs such a serial operation is disclosed in Japanese Laid Open Patent Publication (JP-P2004-318670A). The data processing apparatus includes a first parallel-to-serial conversion circuit, a second parallel-to-serial conversion circuit, a serial operation processing circuit, and a serial-to-parallel conversion circuit. The first parallel-to-serial conversion circuit divides a first parallel data into a predetermined number of first partial data, each of which is composed of a predetermined number of bits, and supplies the predetermined number of the first partial data one by one sequentially. The second parallel-to-serial conversion circuit divides second parallel data to a predetermined number of the second partial data, each of which is composed of a predetermined number of bits, and supplies the predetermined number of the second partial data one by one sequentially. The serial operation processing circuit performs operation processing on the predetermined number of the first partial data sequentially supplied and the predetermined number of the second partial data sequentially supplied for every partial data sequentially for a predetermined number of times. The serial-to-parallel conversion circuit receives a predetermined number of operation results of the operation processing circuit sequentially, combines them into one, and outputs the combination resultant data as a third parallel data.
In the data processing apparatus, both of an operation source data and an operation target data are parallel-to-serial converted, and are all calculated, and the calculation results are outputted. Therefore, an operation time is necessary in proportion to a word length of data subjected to the operation processing. Therefore, the arithmetic the data subjected to the arithmetic operation. If the unit of the operation processing is made small in order to speed up the operation processing, the number of times of the operation processing increases since the operation processing is repeated until the whole processing ends for data of the word length. Therefore, an occupancy time of the data processing apparatus and latency will increase. That is, an amount of data to be processed by the operation processing circuit is always equal to a maximum amount of data determined based on the word length, and for this reason, the reduction in a processing capability and the increase in power consumption are caused, as compared to a case of processing an amount of data, that is effective as data to be actually processed by the operation processing circuit, of the word length of data, i.e., a number of bits.